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Urban Ranger
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Apolyton Duke of Off-Topic
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quote: Originally posted by Asher
I'm still confused why you think that superscalar translates to all execution units in use every cycle. |
That's pretty much is the definition of "supercalar" architecture. Remember all the buzz about how it is more of a "RISC" than "RISC machines?"
If there are three ALUs in the CPU and only a bit more than one microcode is executed per clock cycle, there is something wrong somewhere.
quote: Originally posted by Asher
Even if it were the case that all ALUs were in use, it's not the case that the FPU and SIMD units are in use, which HyperThreading helps fix. |
Okay, if there is a "thread" that doesn't use floating point or SSE/2 instructions, it is theoretically possible to sequeeze more performance out by somehow feeding these units.
quote: Originally posted by Asher
HT is one way to increase ILP, that's why it's there. And it does work in the realworld in most cases, will be improved in Prescott (Prescott doubles much of the logic on the chip in key areas, as well as L1/L2 cache), and adds instructions for thread syncs. |
If the ALU's can't be saturated every cycle, it is a big problem. As I have pointed out previously, this is caused by
quote:
1. The control logic isn't smart enough
2. The execution speed outstrips data transfer speed |
Since logical and integer operations make up the bulk of programs, you can increase IPC a lot more by tackling either [1] or [2].
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